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  1. ║CM:TABLE 2
  2. ║FP
  3.  
  4.  
  5.  
  6. ╘ABLE 3.  ╦EY ╔/╧ ╥EGISTER ╙UMMARY.  (╔NITIAL CONTENTS SHOWN)
  7. -------------------------------------------------------------------------
  8. -----------------$0000---- ╔/╧ ╨╧╥╘ ┴ -----------------------------------
  9. ┬╔╘/╨┴  0  ┬┘╘╙╘┬  ╔N  - ╘IMING SIGNAL; LATCHES DATA INTO ╨╧╥╘ ┬        0
  10.         1  ┴╘╬┴├╦  ╧UT - ┴UTOMATIC ┴╘╬ ACKNOWLEDGE (0=ON/1=OFF)         1
  11.         2  ╔┼┼┴╘╬  ╔N  - ╔┼┼┼ ATTENTION INPUT (INVERTED)                1
  12.         3  ╙┼╥┴╘╬  ╔N  - ╙ERIAL ATTENTION INPUT (INVERTED)              1
  13.         4  ╙┼╥─┴╘  ╔N  - ╙ERIAL DATA INPUT (WHEN ╘╠╦─╔╥=0)              1
  14.         5  ╙┼╥├╠╦  ╔N  - ╙ERIAL CLOCK INPUT (WHEN ╘╠╦─╔╥=0)             1
  15.         6  ╙┘╬├    ╔N  - ╚IGH WHILE A SYNC IS BEING READ                1
  16.         7  ┬┘╘┼╥╤  ╔N  - ─ATA TIMING SIGNAL USED DURING ╥/╫             1
  17. -------------------------------------------------------------------------
  18. -----------------$0001---- ╔/╧ ╨╧╥╘ ┬ -----------------------------------
  19.            (╠ATCHED ╔NPUT ┼N/─ISABLE CONTROLLED BY ═├╥ $0014)   ╠ATCHED  
  20.         ═ODE ├ONTROL - ╙╥╥─┼╬=0 ╔┼┼╙┼╠=1 ╙╘┴╘┼╬=1
  21. ┬╔╘/╨┬  0  ─┴╘┴ ╔/╧                                                     1
  22.         1     "                                                         1
  23.         2     "                                                         1
  24.         3     "           ─╔╙╦ ╥/╫ ╙╚╔╞╘ ╥┼╟╔╙╘┼╥ ╔/╧                   1
  25.         4     "                                                         1
  26.         5     "                                                         1
  27.         6     "                                                         1
  28.         7     "                                                         1
  29. -------------------------------------------------------------------------
  30.         ═ODE ├ONTROL - ╙╥╥─┼╬=1 ╔┼┼╙┼╠=0 ╙╘┴╘┼╬=1    
  31. ┬╔╘/╨┬  0  ─┴╘┴ ╔/╧                                                     1
  32.         1     "                                                         1
  33.         2     "                                                         1
  34.         3     "           ╔┼┼┼ ┬╒╙ ─┴╘┴ ╔╬╨╒╘/╧╒╘╨╒╘                    1
  35.         4     "                                                         1
  36.         5     "                                                         1
  37.         6     "                                                         1
  38.         7     "                                                         1
  39. -------------------------------------------------------------------------
  40.         ═ODE ├ONTROL - ╙╥╥─┼╬=1 ╔┼┼╙┼╠=1 ╙╘┴╘┼╬=0
  41. ┬╔╘/╨┬  0  ─╓╙┼╠0  ╔N  - ─EVICE SELECT JUMPER 0 INPUT                   1
  42.         1  ─╓╙┼╠1  ╔N  - ─EVICE SELECT JUMPER 1 INPUT                   1
  43.         2  ╫╥╘╨╥╘  ╔N  - ╠OW WHEN DISK IN DRIVE IS WRITE PROTECTED      1
  44.         3  ╘╥┴╦00  ╔N  - ╘RACK 0; LOW WHEN HEAD IS AT ╘╥┴├╦ 00          1
  45.         4  (╬OT USED)                                                   1
  46.         5     "                                                         1
  47.         6     "                                                         1
  48.         7     "                                                         1
  49. -------------------------------------------------------------------------
  50. -----------------$0002---- ╔/╧ ╨╧╥╘ ├ -----------------------------------
  51.            (┬US ═ODE ╙ELECT ├ONTROLLED BY ═├╥ $0014)       ╞ULL ┴DDRESS  
  52. ┬╔╘/╨├  0  ─┴╓     ╔/╧  - ╔┼┼┼ 488 ─┴╓ SIGNAL                           1
  53.         1  ┼╧╔     ╔/╧  - ╔┼┼┼ 488 ┼╧╔ SIGNAL                           1
  54.         2  ╬╥╞─    ╔/╧  - ╔┼┼┼ 488 ╬╥╞─ SIGNAL                          0
  55.         3  ╬─┴├    ╔N   - ╔┼┼┼ 488 ╬┴─├ SIGNAL                          0
  56.         4  ╙┼╥├╠╦  ╧╒╘  - ╙ERIAL CLOCK OUTPUT (WHEN ╘╠╦─╔╥=0)           0
  57.         5  ╙┼╥─┴╘  ╧╒╘  - ╙ERIAL DATA OUTPUT (WHEN ╘╠╦─╔╥=0)            0
  58.         6     -         -                                  ┴DDRESS ┴13  1
  59.         7     -         -                                  ┴DDRESS ┴14  1
  60. -------------------------------------------------------------------------
  61. -----------------$0003---- ╔/╧ ╨╧╥╘ ─ -----------------------------------
  62.            (╘RI-╙TATE ┬UFFER CONTROLLED BY ═├╥ $0014)     ╧UTPUT ┴CTIVE  
  63. ┬╔╘/╨─  0  ─╙0          - ─RIVE SELECT 0 (╠OW = ─RIVE 0 ╧N)             1
  64.         1  ─╙2          - ─RIVE SELECT 1 (╠OW = ─RIVE 1 ╧N)             1
  65.         2  ╔┼┼╙┼╠       - (         ╬╧╘┼         )                      1
  66.         3  ╘╠╦─╔╥       - (          --          )                      0
  67.         4  ╙╘╨─╔╥       - (      ╙EE BELOW       )                      1
  68.         5  ╙╘┼╨         - (  FOR DESCRIPTION OF  )                      1
  69.         6  ╫╥╔╘┼╬       - (    THESE SIGNALS     )                      0
  70.         7  ╙╥╥─┼╬       - (          --          )                      0
  71. -------------------------------------------------------------------------
  72.  
  73. ╔╬╨╒╘╙ FOR ╨ORTS ┴, ┬, AND ├ ARE ENABLED BY LOADING LOGIC 1 INTO ALL
  74. REGISTER BIT POSITIONS THAT CORRESPOND TO ╔/╧ INPUT LINES.
  75.  
  76. ╧╒╘╨╒╘ FOR ╨ORTS ┴ THRU ─ ARE CONTROLLED BY WRITING THE DESIRED ╔/╧
  77. LINE OUTPUT STATES INTO THE CORRESPONDING ╔/╧ PORT REGISTER BIT POSITION.
  78. -------------------------------------------------------------------------
  79.  
  80. -----------------$0011---- ╔╬╘┼╥╥╒╨╘ ╞╠┴╟ ╥┼╟╔╙╘┼╥-----------------------
  81. -----------------$0012---- ╔╬╘┼╥╥╒╨╘ ┼╬┴┬╠┼ ╥┼╟╔╙╘┼╥---------------------
  82. ┬╔╘     0  ╨┴ 0 ╨OS EDGE DETECT                                         0
  83.         1  ╨┴ 1 ╨OS EDGE DETECT                                         0
  84.         2  ╨┴ 2 ╬EG EDGE DETECT                                         0
  85.         3  ╨┴ 3 ╬EG EDGE DETECT                                         0
  86.         4  ├OUNTER ┴ UNDERFLOW FLAG                                     1
  87.         5  ├OUNTER ┬ UNDERFLOW FLAG                                     0
  88.         6  ╥├╓╥ FLAG                                                    0
  89.         7  ╪═╘╥ FLAG                                                    0
  90. -------------------------------------------------------------------------
  91.  
  92. -----------------$0014---- ═╧─┼ ├╧╬╘╥╧╠ ╥┼╟╔╙╘┼╥-------------------------
  93. ┬╔╘     0   ├OUNTER ┴ MODE SELECT                                       0
  94.         1     "        "     "                                          0
  95.              ┬IT - 0 1
  96.                    0 0 - ╔NTERVAL TIMER
  97.                    1 0 - ╨ULSE GENERATOR
  98.                    0 1 - ┼VENT COUNTER
  99.                    1 1 - ╨ULSE WIDTH MEAS.
  100.         2  ├OUNTER ┬ ═ODE ╙ELECT                                        0
  101.         3     "        "                                                0
  102.              ┬IT - 2 3
  103.                    0 0 - ╔NTERVAL TIMER
  104.                    1 0 - ╨ULSE GENERATOR
  105.                    0 1 - ┼VENT COUNTER
  106.                    1 1 - ┼XTERNAL TRIGGER
  107.         4  ╨ORT ┬ LATCH                                                 1
  108.         5  ╨ORT ─ TRI-STATE                                             1
  109.         6  ┬US MODE SELECT                                              0
  110.         7   "    "     "                                                0
  111.              ┬IT - 6 7
  112.                    0 0 - ╞ULL ADDRESS MODE
  113.                    1 0 - ╬ORMAL BUS     
  114.                    0 1 - ┴BBR. BUS 
  115.                    1 1 - ═UX'D BUS       
  116. -------------------------------------------------------------------------
  117.  
  118. -----------------$0015---- ╙┼╥╔┴╠ ├╧╬╘╥╧╠ ╥┼╟╔╙╘┼╥-----------------------
  119.                     ( ╬OT USED )
  120. -----------------$0016---- ╙┼╥╔┴╠ ╙╘┴╘╒╙ ╥┼╟╔╙╘┼╥------------------------
  121.                     ( ╬OT USED )
  122. -----------------$0017---- ╙┼╥╔┴╠ ╘/╥ ─┴╘┴ ╥┼╟╔╙╘┼╥----------------------
  123.                     ( ╬OT USED )
  124.  
  125. -----------------$00┴8---- ╚┴╥─╫┴╥┼ ╠┴╘├╚ ($┴000) -----------------------
  126. ┬╔╘     0  ╥/╟╠┼─   - ├ONTROLS POWER ╠┼─ (╙─-2) OR ERROR ╠┼─ (╙─-1)  
  127.         1  ─╥0╠┼─   - ├ONTROLS DRIVE 0 ╠┼─ (╠OW = ╧N, ╙─-2 ╧NLY)     
  128.         2  ─╥1╠┼─   - ├ONTROLS DRIVE 1 ╠┼─ (╠OW = ╧N, ╙─-2 ╧NLY)     
  129.         3  ╙╘┴╘┼╬   - ┼NABLES STATUS CIRCUIT ON ╨╧╥╘ ┬              
  130.         4  ╞╥┼╤┴    - ─ATA DENSITY CONTROL (╠╙┬)                         
  131.         5  ╞╥┼╤┬    - ─ATA DENSITY CONTROL (═╙┬)                         
  132.         6  (╬OT USED)                                                    
  133.         7     "                                                          
  134. -------------------------------------------------------------------------
  135.  
  136. ╙IGNAL     ─ESCRIPTION           
  137. -------------------------------------------------------------------------
  138. ╔┼┼╙┼╠  -  ╔┼┼┼ SELECT.  ╫HEN LOW, THE ╔┼┼┼ ─┴╘┴ BUS IS ACCESSIBLE AT
  139.            ╨╧╥╘ ┬
  140.  
  141. ╘╠╦─╔╥  -  ╘ALK DIRECTION.  ╫HEN LOW THE SERIAL BUS IS ENABLED AND THE
  142.            ╔┼┼┼ CIRCUIT IS IN INPUT MODE (╔┼┼┼ ─┴╘┴, ┼╧╔, ─┴╓ ARE 
  143.            INPUTS; ╬╥╞─ & ╬─┴├ ARE OUTPUTS). ╫HEN HIGH THE SERIAL BUS
  144.            IS DISABLED AND THE ╔┼┼┼ CIRCUIT IS IN OUTPUT MODE
  145.  
  146. ╙╘╨─╔╥  -  ╙TEP DIRECTION CONTROL (LOW = TOWARD ╘RACK 0)
  147.  
  148. ╙╘┼╨    -  ╙TEP SIGNAL TO READ/WRITE HEAD STEP CIRCUIT
  149.  
  150. ╫╥╔╘┼╬  -  ╫RITE ENABLE.  ╫HEN LOW, PUTS THE DRIVE IN THE WRITE MODE
  151.  
  152. ╙╥╥─┼╬  -  ╙HIFT REGISTER READ ENABLE.  ╫HEN LOW, ALLOWS THE ╥/╫ SHIFT
  153.            REGISTER TO BE READ ON ╨╧╥╘ ┬
  154.